REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING
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United States of America Patent
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Issued Date -
Jul 1, 2010
app pub date -
Jun 30, 2009
filing date -
Dec 30, 2008
priority date (Note) -
Abandoned
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Abstract
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
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