APPARATUS AND METHOD FOR TESTING A TRANSDUCER AND/OR ELECTRONIC CIRCUITRY ASSOCIATED WITH A TRANSDUCER
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United States of America Patent
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Issued Date -
Jul 1, 2010
app pub date -
Dec 30, 2009
filing date -
Dec 30, 2008
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Abandoned
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Abstract
A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path.
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