System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes
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United States of America Patent
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Issued Date -
Jun 24, 2010
app pub date -
Dec 23, 2008
filing date -
Dec 23, 2008
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Abandoned
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Abstract
An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means assigns threads to the processing cores of the given processing element in a configurable manner. The configuration of the thread scheduling means defines one or more logical symmetric multiprocessors for executing threads on the given processing element. A logical symmetric multiprocessor is realized by a defined set of processing cores assigned to a group of threads executing on the given processing element.
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