REDUCTION OF POWER CONSUMPTION IN A MEMORY DEVICE DURING SLEEP MODE OF OPERATION
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United States of America Patent
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Issued Date -
Jun 17, 2010
app pub date -
Nov 11, 2009
filing date -
Nov 11, 2008
priority date (Note) -
Abandoned
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Abstract
The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system.
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