HIERARCHICAL SHARED SEMAPHORE REGISTERS
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United States of America Patent
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Issued Date -
May 6, 2010
app pub date -
Oct 31, 2008
filing date -
Oct 31, 2008
priority date (Note) -
Abandoned
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Abstract
A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.
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