Circuit with a memory array and a reference level generator circuit

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United States of America Patent

PATENT NO 8081523
APP PUB NO 20100103751A1
SERIAL NO

11813862

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.

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Patent Owner(s)

Patent OwnerAddress
MORGAN STANLEY SENIOR FUNDING INC1300 THAMES STREET 4TH FLOOR BALTIMORE MD 21231

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lambert, Nicolaas Waalre, NL 100 1412
Van, Acht Victor Martinus Waalre, NL 5 21
Woerlee, Pierre Hermanus Valkenswaard, NL 58 436

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