Circuits and methods for buffering and communicating data signals
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United States of America Patent
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Jun 28, 2011
Grant Date -
Apr 29, 2010
app pub date -
Jan 5, 2010
filing date -
Feb 24, 2006
priority date (Note) -
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Abstract
Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.
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