ARITHMETIC-LOGIC UNIT FOR DIGITAL SIGNAL PROCESSOR
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United States of America Patent
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Issued Date -
Apr 22, 2010
app pub date -
Oct 22, 2009
filing date -
Oct 22, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
An arithmetic-logic unit for a digital signal processor, processing audio signals, having a multiplier circuit able to receive in input a first and a second signal and to supply in output a third signal which represents the result of the multiplication of said first and second signal, a generator circuit of a dither signal, a summation circuit downline of the multiplier circuit, said summation circuit being able to perform an addition operation between said third signal and the dither signal so as to supply a fourth signal in output, and a truncation or rounding circuit downline of the summation circuit, able to truncate or round said fourth signal.
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