A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements. When the active edge has arrived at each of the selection gates, each is held in an output state until the input to the selection gates becomes inactive, even if the selection signals changes.

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