HARDWARE TRIGGERED DATA CACHE LINE PRE-ALLOCATION

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United States of America Patent

APP PUB NO 20100077151A1
SERIAL NO

12523388

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Abstract

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A computer system includes a data cache supported by a copy-back buffer and pre-allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register is requested for pre-allocation. Bunches of pre-allocation requests are organized and scheduled by the pre-allocation request stack, and will take their turns to allow the cache lines being replaced to be processed through the copy-back buffer. By the time the processor gets to doing the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles.

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Patent Owner(s)

Patent OwnerAddress
MORGAN STANLEY SENIOR FUNDING INC1300 THAMES STREET 4TH FLOOR BALTIMORE MD 21231

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Van, De Waerdt Jan Willem San Jose, US 7 71

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