Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups
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United States of America Patent
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Issued Date -
Mar 11, 2010
app pub date -
Sep 10, 2008
filing date -
Sep 10, 2008
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Abstract
A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated.
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