THREE-DIMENSIONAL STRUCTURAL SEMICONDUCTOR DEVICE
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United States of America Patent
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Issued Date -
Feb 25, 2010
app pub date -
Mar 28, 2008
filing date -
Mar 29, 2007
priority date (Note) -
Abandoned
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Abstract
A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection.
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