METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY
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United States of America Patent
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Issued Date -
Jan 28, 2010
app pub date -
Jul 23, 2008
filing date -
Jul 23, 2008
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Abandoned
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Abstract
A method for preparing a multi-level flash memory comprising the steps of forming a recess in a semiconductor substrate, forming a plurality of storage structures at the sides of the recess, and forming a gate structure having a lower block in the recess and an upper block on the lower block. The storage structures are separated by the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site.
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