MULTI-LEVEL FLASH MEMORY
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United States of America Patent
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Issued Date -
Jan 28, 2010
app pub date -
Jul 23, 2008
filing date -
Jul 23, 2008
priority date (Note) -
Abandoned
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Abstract
A multi-level flash memory comprises a semiconductor substrate, a gate structure having a lower block positioned in the semiconductor substrate and an upper block positioned on the semiconductor substrate, and a plurality of storage structures separated by the gate structure. The upper block connects to the lower block of the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site.
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