MULTI-LEVEL FLASH MEMORY STRUCTURE
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United States of America Patent
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Issued Date -
Jan 28, 2010
app pub date -
Jul 23, 2008
filing date -
Jul 23, 2008
priority date (Note) -
Abandoned
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Abstract
A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.
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