NON-VOLATILE MEMORY CELL WITH A HYBRID ACCESS TRANSISTOR
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United States of America Patent
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app pub date -
Sep 24, 2009
filing date -
Apr 27, 2007
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Abandoned
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Abstract
An integrated circuit (IC) is disclosed. The IC comprises a substrate with a cell region defined thereon. The cell region comprises a thin gate doped well tailored for transistors with thin gate dielectric layers. The IC also includes a non-volatile memory cell in the cell region. The non-volatile memory cell has an access transistor and a storage transistor. The access transistor includes an access gate with an access gate dielectric comprising a thick gate dielectric layer on the thin gate doped well. Wells for transistors with thick gate dielectric layers have a lower dopant concentration than the thin gate doped well.
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