INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR WELL FORMATION

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United States of America Patent

APP PUB NO 20100009527A1
SERIAL NO

12172724

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Abstract

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A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate.

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CHARTERED SEMICONDUCTOR MANUFACTURING LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 73840

International Classification(s)

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  • 2008 Application Filing Year
  • H01L Class
  • 14823 Applications Filed
  • 10962 Patents Issued To-Date
  • 73.96 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances200820092010201120122013201420152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gao, Wenzhi Singapore, SG 11 136
Hsia, Liang-Choo Singapore, SG 53 849
Lai, Chung Woh Singapore, SG 30 238
Lee, Yong Meng Singapore, SG 49 431
Liu, Huang Singapore, SG 123 799
Lun, Zhao Singapore, SG 24 335
Mishra, Shailendra Singapore, SG 57 2745
Widodo, Johnny Singapore, SG 31 472

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  • 2 Citation Count
  • H01L Class
  • 2.46 % this patent is cited more than
  • 15 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges10417069704922861911147665453015101 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0100200300400500600700800900100011001200130014001500160017001800

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