Method for Inter-Router Dual-Function Energy- and Area-Efficient Links for Network-on-Chips

United States of America Patent

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Issued Date
Jan 7, 2010
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Apr 6, 2009
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Apr 4, 2008

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Abstract

The present invention provides methods for connecting routers and transmitting data along inter-router links within Nework-on-Chip (NoC) architectures.

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Patent Owner	Address
THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA	THE UNIVERSITY OF ARIZONA TECH TRANSFER ARIZONA UNIVERSITY SERVICES ANNEX 4TH FLOOR PO BOX 210300A TUCSON AS 85721

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H04L:TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAP....

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Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Kodi, Avinash K	Athens, US	3	5
Louri, Ahmed	Tucson, US	11	29
Roveda, Janet Meiling Wang	Tucson, US	3	5
Sarathy, Ashwini	Hillsboro, US	3	5

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Method for Inter-Router Dual-Function Energy- and Area-Efficient Links for Network-on-Chips

Number of patents in Portfolio can not be more than 2000

United States of America Patent

12418701

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12418701

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