METHOD AND APPARATUS FOR SHARING MEMORY
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United States of America Patent
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Issued Date -
Jan 7, 2010
app pub date -
Jul 27, 2007
filing date -
Jul 28, 2006
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A digital processing apparatus using a memory sharing structure through a bypass logic and a sharing method thereof are disclosed. According to an embodiment of the present invention, the digital processing apparatus includes an application processor, a supplementary memory unit, which is subordinate to the application processor, and a main processor, which controls the application processor. If no communication is made using a control bus between the main processor and the application processor, the application processor connects a route to allow the main processor and the supplementary memory unit to be directly coupled to each other by executing a predetermined bypass logic. Through this, the capacity of a useable memory of the main processor can be maximized.
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