CHIP PACKAGE WITH ESD PROTECTION STRUCTURE
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United States of America Patent
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Issued Date -
Jan 7, 2010
app pub date -
Jul 3, 2008
filing date -
Jul 3, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.
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