PFET ENHANCEMENT DURING SMT
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United States of America Patent
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Issued Date -
Dec 10, 2009
app pub date -
Jun 5, 2008
filing date -
Jun 5, 2008
priority date (Note) -
Abandoned
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Abstract
An integrated circuit having a substrate on which first and second active regions are defined. The first active region comprises a first transistor and the second active region comprises a second transistor having a first type stress. A barrier layer is provided over the substrate to reduce outdiffusion of dopants in the first active region.
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