Method of manufacturing a semiconductor device
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United States of America Patent
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Apr 26, 2011
Grant Date -
Nov 19, 2009
app pub date -
May 19, 2009
filing date -
May 19, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
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