FOUR-TERMINAL MULTIPLE-TIME PROGRAMMABLE MEMORY BITCELL AND ARRAY ARCHITECTURE
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United States of America Patent
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Issued Date -
Nov 5, 2009
app pub date -
Apr 30, 2009
filing date -
Apr 30, 2008
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Abstract
Embodiments disclosed herein relate to a non-volatile memory bitcell and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell is in an erased state, methods of setting the bitcell in a programmed state and methods of setting the bitcell in an erased state. The non-volatile memory bitcell may be a four terminal bitcell. The bitcell may have a pull-up electrode, a pull-down electrode, a cantilever electrode and a contact electrode. An NMOS transistor may be coupled to the contact electrode. Depending upon the orientation of the word line, the current through the bitcell may be measured on the bitline, the data line or the pull-down electrode.
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