High-Speed Video Serializer and Deserializer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Oct 22, 2009
app pub date -
Apr 2, 2009
filing date -
Apr 4, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such that a frequency of the signals on the output bus is a multiple of the frequency of the signals on the input bus. A circuit provides a clock signal substantially in sync with the signals on the output bus. A high speed video deserializer is also disclosed as are methods of operating the serializer and deserializer.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully