NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTS
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United States of America Patent
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Issued Date -
Oct 8, 2009
app pub date -
Apr 3, 2008
filing date -
Apr 3, 2008
priority date (Note) -
Abandoned
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Abstract
Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.
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