PCB layout structrue for suppressing EMI and method thereof
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United States of America Patent
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Issued Date -
Oct 1, 2009
app pub date -
Apr 1, 2008
filing date -
Apr 1, 2008
priority date (Note) -
Abandoned
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Abstract
A PCB layout structure for suppressing EMI and a method thereof is disclosed. The PCB layout structure for suppressing EMI includes a multi-layer PCB, a plurality of electric grids, and a plurality of conductive vias. The multi-layer PCB has a plurality of signal layers and a grounding layer. Each of the signal layers is disposed with a plurality of signal lines. The plurality of electric grids are disposed on each of the signal layers and cover the signal lines on each of the signal layers. The plurality of conductive vias are located between the layers of the multi-layer PCB to electrically connect the grounding layer with the electric grids on each of the signal layers. Thereby, electromagnetic waves of a specific wavelength are shielded by appropriately choosing the dimensions of the electric grids.
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