METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Oct 1, 2009
app pub date -
Mar 26, 2009
filing date -
Mar 28, 2008
priority date (Note) -
Abandoned
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Abstract
A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.
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