METHOD AND SYSTEM FOR PROCESSING TEST WAFER IN PHOTOLITHOGRAPHY PROCESS
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United States of America Patent
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Issued Date -
Sep 24, 2009
app pub date -
Apr 30, 2008
filing date -
Mar 24, 2008
priority date (Note) -
Abandoned
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Abstract
A method and a system for processing a test wafer in a photolithography process are provided for processing an ith layer of the test wafer, and i is a positive integer. In the present method, a compensation value is calculated according to historical compensation behaviors of an equipment, relationships between the ith layer and other layers, and offsets generated in performing a non-photolithography process on the test wafer. Then, the test wafer is processed according to the compensation value. A determination on whether the test wafer meets a design specification is then made. Rework is performed on the test wafer if the test wafer does not meet the design specification. Accordingly, an adjustable compensation value is used to process the test wafer and avoid unnecessary rework. The possibility of rework on the test wafer is reduced so as to increase the efficiency of the photolithography process.
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