NAND TYPE NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF
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United States of America Patent
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Issued Date -
Sep 24, 2009
app pub date -
Mar 24, 2008
filing date -
Mar 24, 2008
priority date (Note) -
Abandoned
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Abstract
A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line.
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