INTEGRATED CIRCUIT THAT SELECTIVELY OUTPUTS SUBSETS OF A GROUP OF DATA BITS
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United States of America Patent
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Issued Date -
Sep 10, 2009
app pub date -
Mar 5, 2008
filing date -
Mar 5, 2008
priority date (Note) -
Abandoned
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Abstract
An integrated circuit including an array of memory cells, a control circuit, and an output circuit. The array of memory cells is configured to provide a group of data bits. The control circuit is configured to provide a test mode signal. The output circuit is configured to receive the test mode signal and the group of data bits, where the output circuit selectively outputs smaller subsets of the group of data bits based on the test mode signal.
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