SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME
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United States of America Patent
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N/A
Issued Date -
Sep 10, 2009
app pub date -
Mar 10, 2009
filing date -
Mar 10, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A power MOSFET exhibits a high breakdown voltage and low ON-state resistance. The device includes a trench formed in a semiconductor substrate, a gate electrode located along a side wall of the trench and a bottom wall of the trench near a side wall thereof, a pillar section, a first drain region of a first conductivity type in the pillar section, a base region of a second conductivity type in contact with the side wall of the trench in a bottom portion thereof and the bottom wall of the trench, a source region of the first conductivity type in a surface portion of the base region, a RESURF region of the second conductivity type in the pillar section, the RESURF region being formed in contact with the first drain region; and a second drain region of the first conductivity type in a side wall surface portion of the pillar section.

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- 15 United States
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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FUJI ELECTRIC SYSTEMS CO LTD | 11-2 OSAKI 1-CHOME SHINAGAWA-KU TOKYO 141-0032 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
KITAMURA, Mutsumi | Matsumoto City , JP | 23 | 267 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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