Strained Channel PMOS Transistor and Corresponding Production Method
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United States of America Patent
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Issued Date -
Aug 20, 2009
app pub date -
Apr 1, 2005
filing date -
Apr 1, 2005
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Abandoned
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Abstract
The PMOS transistor (TR) has a channel width W of less than 1 micrometer, a channel length of less than or equal to 0.1 micrometer, and a distance of more than 0.5 micrometer between one edge of the channel and the corresponding edge of the active zone. The production of the active zone includes epitaxy on a first semiconductor material (SB) of an intermediate layer (CI) formed by a second semiconductor material having a lattice parameter greater than that of the first material, and epitaxy on the intermediate layer (CI) of an upper layer (CS) formed by the first material, anisotropic etching (GR) of the upper layer and the intermediate layer on either side of the two sidewalls of the gate region, and filling of the recesses thus formed by epitaxy (EPX) of the first material.
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