PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME
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United States of America Patent
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Issued Date -
Aug 13, 2009
app pub date -
Jan 11, 2007
filing date -
Jan 12, 2006
priority date (Note) -
Abandoned
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Abstract
The phase comparison circuit according to an embodiment of the present invention comprises a fractional frequency divider 31 which generates a fractional frequency-divided signal Svn obtained by performing fractional frequency division on a clock on the basis of a control signal from a control circuit 32, a first integer frequency divider 33 which generates a first integer frequency-divided signal obtained by performing integer frequency division on the fractional frequency-divided signal Svn, a second integer frequency divider 34 which generates a second integer frequency-divided signal obtained by performing integer frequency division on a reference clock, a first selection circuit 35 which selectively outputs either the fractional frequency-divided signal Svn or the first integer frequency-divided signal on the basis of a switching signal, a second selection circuit 36 which selectively outputs either the reference clock or the second integer frequency-divided signal on the basis of the switching signal from the control circuit 32, and a phase comparator 37 which generates a comparison signal which represents the frequency difference and phase difference between the output signal from the first selection circuit 35 and the output signal from the second selection circuit 36.
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