Method and Apparatus for MOSFET Drain-Source Leakage Reduction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Mar 6, 2009
filing date -
Feb 12, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A method and apparatus are taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS logic gate, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. The first transistor's gate is controlled by a digital voltage source having a same polarity as that of an output of the CMOS logic gate and the second transistor is controlled by a digital voltage source having a same polarity as that of an input to the CMOS logic gate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully