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Abstract

A plasma display panel capable of reducing further a surface discharge voltage without additionally providing a process leading to cost increase, and contributing to the reduction in address discharge delay. The plasma display panel comprises an electrode group of an X electrode and a Y electrode consisting of adjacent transparent electrodes disposed in parallel to a front plate and forming gaps discharging at a specified gap and bus electrodes thicker than the transparent electrodes, lower in electric resistance, and electrically connected to the transparent electrodes, a dielectric layer and a protective layer covering the electrode group of the X electrode and the Y electrode, and an electrode group of address electrodes disposed on a rear plate disposed facing the front plate and in a direction perpendicular to the electrode group of the X electrode and the Y electrode, wherein the bus electrodes (16) are disposed continuously from the one end to the vicinity of the other end of the front plate (1) and away from the discharge edge of the transparent electrode (15), and the discharging edge of the transparent electrode (15) is provided with a separation bus (17) thicker than the transparent electrode (15) so as to let the dielectric layer (13) on the front plate (1) have a surface shape reflecting unevenness resulting from the thicknesses of the bus electrode (16) and the separation bus (17) on the front plate (1), whereby it is possible to form a recessed portion (18) resulting from the separation bus (17) in a gap portion.

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First Claim