STACK CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Jul 30, 2009
app pub date -
May 13, 2008
filing date -
Jan 28, 2008
priority date (Note) -
Abandoned
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Abstract
A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.
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