Split-gate non-volatile memory devices having nitride tunneling layers
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jul 23, 2009
app pub date -
Jan 22, 2008
filing date -
Jan 22, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully