INTEGRATED CIRCUIT WITH REDUCED POINTER UNCERTAINLY
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United States of America Patent
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Issued Date -
Jul 16, 2009
app pub date -
Jan 15, 2008
filing date -
Jan 15, 2008
priority date (Note) -
Abandoned
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Abstract
One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a selected clock from multiple clocks based on the sample. The second circuit is configured to provide a first pointer clock based on the first clock and a second pointer clock based on the selected clock. An edge of the second pointer clock relative to an edge of the first pointer clock is limited to an uncertainty range of within one-half a first pointer clock cycle.
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