PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT
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United States of America Patent
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N/A
Issued Date -
Jul 2, 2009
app pub date -
Dec 19, 2008
filing date -
Dec 31, 2007
priority date (Note) -
Abandoned
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Abstract
A package substrate embedded with a semiconductor component is provided. A semiconductor chip is received in a cavity of a substrate body, and has electrode pads on an active surface thereof. A passivation layer is disposed on the active surface and has openings for exposing the electrode pads. An electroless plating metal layer, a first sputtering metal layer and a second sputtering metal layer are sequentially formed on the electrode pads, the openings of the passivation layer and the passivation layer surface around the openings. Contact pads are formed on the second sputtering metal layer. A first dielectric layer is disposed on the substrate body and the passivation layer. A first circuit layer is formed on the first dielectric layer. First conductive vias are formed in the first dielectric layer and electrically connected to the contact pads. The first circuit layer is electrically connected to the first conductive vias.
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