INTEGRATED DEVICE TECHNOLOGY USING A BURIED POWER BUSS FOR MAJOR DEVICE AND CIRCUIT ADVANTAGES
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United States of America Patent
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app pub date -
Feb 7, 2007
filing date -
Dec 28, 2001
priority date (Note) -
Abandoned
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Abstract
A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB).
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