HI-FIX BOARD, TEST TRAY, TEST HANDLER, AND METHOD FOR MANUFACTURING PACKAGED CHIPS
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United States of America Patent
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Issued Date -
Jun 18, 2009
app pub date -
Dec 4, 2008
filing date -
Dec 13, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A hi-fix board, a test tray, a test handler, and a packaged chip manufacturing method are provided. The hi-fix board includes: test sockets to which packaged chips to be tested are connected; and a main frame in which the test sockets are disposed in at least one first area to form an a×b matrix (where a and b are integers greater than 0) and the test sockets are disposed in at least one second area to form a c×d matrix (where c is an integer greater than a and d is an integer greater than 0). By allowing the test tray to contain more packaged chips at a time and minimizing a difference in length between a horizontal direction and a vertical direction, it is possible to reduce the index time. By allowing all the packaged chips contained in a test tray to be subjected to a testing process at the same time, it is possible to reduce the time for the testing process and to enhance the stability.
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