DYNAMIC-BASED VERIFICATION APPARATUS FOR VERIFICATION FROM ELECTRONIC SYSTEM LEVEL TO GATE LEVEL, AND VERIFICATION METHOD USING THE SAME
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United States of America Patent
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Issued Date -
Jun 11, 2009
app pub date -
Oct 10, 2006
filing date -
Oct 10, 2005
priority date (Note) -
Abandoned
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Abstract
In this invention, the instrumentation circuit or instrumentation code is added to the original design by the verification software, which is executed in a computer. The simulation consists of a front-end simulation and a back-end simulation. The front-end simulation can use an equivalent model at different abstraction level, or a simulation model for the back-end simulation. The back-end simulation uses the simulation result of front-end simulation so that it can run one or more simulation runs sequentially or in parallel. Or models at lower level of abstraction are simulated together with a model at higher level of abstraction in parallel using two or more simulators.Also, the debugging method with high visibility and controllability for the verification using a physical prototype in the in-circuit or in-system environment is provided by simulation using a simulator or a virtual prototype, and the dynamic information collected from a physical prototype in real time.
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