SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF
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United States of America Patent
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Issued Date -
Jun 11, 2009
app pub date -
Apr 29, 2008
filing date -
Dec 10, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the top surface of the substrate so as to cover at least partially the conductive post and the semiconductor chip; and an external connection bump electrically connected to the conductive post. The system-in-package is fabricated by stacking a plurality of semiconductor chips on a top surface of a base wafer, forming a buried layer, realizing an electrical path by a conductive post, and polishing top and bottom surfaces of the package, thereby thinning the thickness of the package. Further, the system-in-package greatly improves electrical operation characteristics and increases productivity.
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