Trench mosfet and manufacturing method thereof
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United States of America Patent
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Issued Date -
May 21, 2009
app pub date -
Nov 18, 2008
filing date -
Nov 19, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
This invention relates to a trench MOSFET, which can lower parasitic capacitance, thereby increasing a switching speed, and to a method of manufacturing the trench MOSFET. The trench MOSFET includes a substrate having an epi layer and a body layer sequentially formed thereon, a trench formed vertically in the central portion of the epi layer and the body layer, a first gate oxide film formed on the inner wall of the trench, a diffusion oxide film formed in the epi layer between the lower surface of the trench and the upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench, a gate formed in the trench having the first gate oxide film, a second gate oxide film formed on the gate, and a source region formed at both sides of the upper portion may be of the gate, thus reducing the generation of parasitic capacitance between the epi layer corresponding to a drain region and the gate, thereby improving a switching speed.
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