BGA package with traces for plating pads under the chip
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United States of America Patent
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Nov 8, 2011
Grant Date -
May 7, 2009
app pub date -
May 21, 2008
filing date -
Nov 1, 2007
priority date (Note) -
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Abstract
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.
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