PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN
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United States of America Patent
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app pub date -
Oct 17, 2008
filing date -
Oct 17, 2007
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Abstract
Source and/or drain regions of a transistor are first doped with an appropriate dopant and a metal is subsequently deposited. After heating, a silicide will displace the dopant, creating an increased density of dopants at the border of the silicided region. The dopants that are adjacent to or in the gate region of the device will form a thin layer. The silicide or other reactant material is then removed and replaced with a desired source/drain material, while leaving the layer of dopant immediately adjacent to the newly deposited source/drain material.
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