MEMORY DEVICES WITH SPLIT GATE AND BLOCKING LAYER
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United States of America Patent
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Issued Date -
Apr 23, 2009
app pub date -
Oct 22, 2007
filing date -
Oct 22, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.
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