NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE
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United States of America Patent
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Issued Date -
Apr 16, 2009
app pub date -
Oct 16, 2007
filing date -
Oct 16, 2007
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Abandoned
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Abstract
A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer (160) and at least 20% of the charge in a floating gate (170). The floating gate is at most 20 nm thick.
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