Multi-layer electrode, cross point memory array and method of manufacturing the same
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United States of America Patent
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Issued Date -
Apr 16, 2009
app pub date -
Jun 5, 2008
filing date -
Oct 10, 2007
priority date (Note) -
Abandoned
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Abstract
Provided may be a multi-layer electrode, a cross point resistive memory array and method of manufacturing the same. The array may include a plurality of first electrode lines arranged parallel to each other; a plurality of second electrode lines crossing the first electrode lines and arranged parallel to each other; and a first memory resistor at intersections between the first electrode lines and the second electrode lines, wherein at least one of the first electrode lines and the second electrode lines have a multi-layer structure including a first conductive layer and a second conductive layer formed of a noble metal.
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