NAND-type Flash Array with Reduced Inter-cell Coupling Resistance
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United States of America Patent
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Issued Date -
Apr 2, 2009
app pub date -
Sep 27, 2007
filing date -
Sep 27, 2007
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Abandoned
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Abstract
In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of the inter-cell coupling region. The diffusion zone includes a shallow implant region and a deep implant region. In one embodiment, the shallow implant region defines shallow source/drain regions for floating gate transistors of the memory cells. The size of the metal silicide insets are controlled to not compromise isolation PN junctions defined by the shallow and deep implant region. In one embodiment, the metal silicide insets include nickel.
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